An Energy-Efficient Neuromorphic Processor Using Unified Refractory Control-Based NoC for Edge AI

Neuromorphic computing has emerged as a promising paradigm for edge AI systems owing to its event-driven operation and high energy efficiency. However, conventional spiking neural network (SNN) architectures often suffer from redundant computation and inefficient power control, particularly during on-chip learning. This paper proposes a network-on-chip (NoC) architecture featuring a unified refractory-enabled neuron (UREN)-based router that globally coordinates spike-driven computation across multiple neuron cores. The router applies a unified refractory time to all neurons following a winner spike event, effectively enabling clock gating and suppressing redundant activity. The proposed design adopts a star-routing topology with multicasting support and integrates nearest-neighbor spike-timing-dependent plasticity (STDP) for local online learning. FPGA-based experiments demonstrate a 30% reduction in computation and 86.1% online classification accuracy on the MNIST dataset compared with baseline SNN implementations. These results confirm that the UREN-based router provides a scalable and power-efficient neuromorphic processor architecture, well suited for energy-constrained edge AI applications.

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Publication Details

Journal
Electronics
Published
2025-12-17
DOI
https://doi.org/10.3390/electronics14244959
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.00

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article

An Energy-Efficient Neuromorphic Processor Using Unified Refractory Control-Based NoC for Edge AI

S. Na Sangkwon Na, Dong–Sun Kim
Electronics
Advanced Memory and Neural Computing
article

An Energy-Efficient Neuromorphic Processor Using Unified Refractory Control-Based NoC for Edge AI

S. Na Sangkwon Na, Dong–Sun Kim
article en

Abstract

Neuromorphic computing has emerged as a promising paradigm for edge AI systems owing to its event-driven operation and high energy efficiency. However, conventional spiking neural network (SNN) architectures often suffer from redundant computation and inefficient power control, particularly during on-chip learning. This paper proposes a network-on-chip (NoC) architecture featuring a unified refractory-enabled neuron (UREN)-based router that globally coordinates spike-driven computation across multiple neuron cores. The router applies a unified refractory time to all neurons following a winner spike event, effectively enabling clock gating and suppressing redundant activity. The proposed design adopts a star-routing topology with multicasting support and integrates nearest-neighbor spike-timing-dependent plasticity (STDP) for local online learning. FPGA-based experiments demonstrate a 30% reduction in computation and 86.1% online classification accuracy on the MNIST dataset compared with baseline SNN implementations. These results confirm that the UREN-based router provides a scalable and power-efficient neuromorphic processor architecture, well suited for energy-constrained edge AI applications.

ElectronicsVol. 14(24)
Sejong University (KR)
Iran Telecommunication Research Center, Ministry of Science and ICT, South Korea, Institute for Information and Communications Technology Promotion
Openalex Percentile: Top 59%
Advanced Memory and Neural Computing
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