A self-calibration of RDAC mismatch compensation technique for high-resolution SAR ADC design

Battery management system as core components of mobile power supplies and energy storage systems, rely critically on the precision of their analog-to-digital converters (ADCs) to optimize battery performance. This paper addresses resistor mismatch issues in resistor DACs for battery management chip ADC, arising from process variations, proposing an adaptive calibration method. The approach dynamically compares voltages of resistors under calibration with reference resistor-divided voltages, utilizing successive approximation logic to control series/parallel trimming resistors and mitigate mismatch induced accuracy degradation. Based on the 0.35μm commercial BCD process, a 12-bit, 20kPS SAR ADC for a battery management chip has been designed and comprehensively verified. The verification results shows that, under actual process variations, the adaptive calibration method reduces the DNL range from -2.7 +3.3 LSB to -0.3 +0.4 LSB, and the INL range from -2.2 +2.7 LSB to -0.3 +0.4 LSB. ENOB achieves 11.22 bits, SINAD reaches 69.33 dB, SFDR is 74.98 dB.