Sub-50-mV Extremely Low-Voltage Flip-Flop Circuit Consisting of Recursive Stacking Body-Bias CMOS Logic Gates

This paper proposes an extremely low-voltage flip-flop (ELVFF) consisting of recursive stacking body-bias (RSBB) logic gates. The ELVFF has the capability of operating at extremely low supply voltages. The ELVFF is based on a conventional NAND latch-based flip-flop (NLFF) and consists of three-times RSBB NANDs (3RSBB-NANDs) and one-time RSBB inverters (1RSBB-INVs). These techniques will provide a promising solution for achieving ELV operation. These techniques enhances both the voltage swing and voltage gain of logic gates, enabling the ELVFF to operate at extremely low supply voltages. Simulation results in a 0.18-μm CMOS process technology with a deep n-well option showed that the proposed ELVFF can operate at an extremely low supply voltage, below 50 mV. Measurement results also demonstrated that the ELVFF can latch and retain the correct logic data with a voltage swing of 27 mV at a 44-mV power supply. The proposed ELVFF is suitable for sub-100-mV ELV applications, such as energy harvesting, at the cost of an increased number of transistors, area, power, and delay time.