Analog In-Memory Computing from a Memory-Agnostic Perspective: Theory, Nonidealities, and Hardware-Aware Training
Analog in-memory computing (AIMC) executes matrix-vector multiplications (MVMs) inside memory to alleviate the von Neumann bottleneck and improve energy efficiency. This tutorial classifies AIMC circuits in a memory-agnostic way, namely, current-domain, charge-domain, charge-redistribution, capacitive-division, resistive-division, and time-domain IMC. We explain each type of AIMC circuit with simple mathematical models. Furthermore, we review key device and circuit nonidealities (e.g., process variation, IR drop, sneak paths, and I/O quantization/ nonlinearity) with practical mitigation strategies in circuitry and peripherals. Finally, we organize hardware-aware training into three complementary families—probabilistic/precise modeling, physical modeling, and hardware-in-the-loop techniques—providing a mathematically grounded bridge between circuits and learning for robust, scalable AIMC accelerators.
Authors
- Hiromitsu Awano (ORCID: https://orcid.org/0000-0002-3674-4584)
- Yusuke Sakemi (ORCID: https://orcid.org/0000-0002-0274-9491)
- Takashi Morie (ORCID: https://orcid.org/0000-0003-2708-4307)
Institutions
- Kyushu Institute of Technology (JP)
- Kyoto University (JP)
- Tokyo International University (JP)
- Chiba Institute of Technology (JP)
Publication Details
- Journal
- IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1587/transfun.2025gci0001
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- Japan Society for the Promotion of Science
- Precursory Research for Embryonic Science and Technology