Dialga: A Family of Low-Latency Tweakable Block Ciphers Using Multiple Linear Layers

In this paper, we propose Dialga, a family of low-latency tweakable block ciphers designed to support 128/256-bit tweaks and 256-bit keys. Dialga achieves significantly small latency by leveraging multiple novel strategies. These include the use of multiple linear layers with efficient cell permutations, which enhance security against differential and linear attacks with negligible hardware overhead. We also identify the optimal choice of S-boxes for these permutations using state-ofthe- art evaluation methods by SAT, enabling us to further reduce the delay of the round function. Besides, we design a reflection tweakey schedule that ensures strong security in the related-tweak setting and allows for encryption and decryption without delay overhead, reducing the circuit area. We conducted comprehensive hardware benchmarks involving Dialga and other primitives. As a result, Dialga achieves nearly half the delay of QARMAv2, while achieving approximately a 40% reduction in area, with the same claimed security.

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Publication Details

Journal
IACR Transactions on Symmetric Cryptology
Published
2025-12-17
DOI
https://doi.org/10.46586/tosc.v2025.i4.70-124
Primary Topic
Cryptographic Implementations and Security
Type
article
Field-Weighted Citation Impact
0.00

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article

Dialga: A Family of Low-Latency Tweakable Block Ciphers Using Multiple Linear Layers

Kiyoshi Nakata, Subhadeep Banik, Kosei Sakamoto, Kazuhiko Minematsu et al.
IACR Transactions on Symmetric Cryptology
Cryptographic Implementations and Security
article

Dialga: A Family of Low-Latency Tweakable Block Ciphers Using Multiple Linear Layers

Kiyoshi Nakata, Subhadeep Banik, Kosei Sakamoto, Kazuhiko Minematsu, Ryoma Ito, Mostafizar Rahman, Takanori Isobe, Ishikawa Tatsuya
article en

Abstract

In this paper, we propose Dialga, a family of low-latency tweakable block ciphers designed to support 128/256-bit tweaks and 256-bit keys. Dialga achieves significantly small latency by leveraging multiple novel strategies. These include the use of multiple linear layers with efficient cell permutations, which enhance security against differential and linear attacks with negligible hardware overhead. We also identify the optimal choice of S-boxes for these permutations using state-ofthe- art evaluation methods by SAT, enabling us to further reduce the delay of the round function. Besides, we design a reflection tweakey schedule that ensures strong security in the related-tweak setting and allows for encryption and decryption without delay overhead, reducing the circuit area. We conducted comprehensive hardware benchmarks involving Dialga and other primitives. As a result, Dialga achieves nearly half the delay of QARMAv2, while achieving approximately a 40% reduction in area, with the same claimed security.

IACR Transactions on Symmetric CryptologyVol. 2025(4)
NEC (Japan) (JP), University of Hyogo (JP), Kyoto University (JP), Mitsubishi Electric (Japan) (JP), Università della Svizzera italiana (CH), The University of Osaka (JP)
Small Business Innovation Research, Japan Society for the Promotion of Science
Openalex Percentile: Top 78%
Cryptographic Implementations and Security
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