BEANIE – A 32-bit Cipher for Cryptographic Mitigations Against Software Attacks

In modern CPU architectures, various security features to mitigate software attacks can be found. Examples of such features are logical isolation, memory tagging or shadow stacks. Basing such features on cryptographic isolation instead of logical checks can have many advantages such as lower memory overhead and more robustness against misconfiguration or low-cost physical attacks. The disadvantage of such an approach is however that the cipher that has to be introduced has a severe impact on the system performance, either in terms of additional cycles or a decrease of the maximum achievable frequency. Finally, as of today, there is no suitable low-latency cipher design available for encrypting 32-bit words as is common in microcontrollers. In this paper, we propose a 32-bit tweakable block cipher tailored to memory encryption for microcontroller units. We optimize this cipher for low latency, which we achieve by a careful selection of components for the round function and leveraging an attack scenario similar to the one used to analyze the cipher SCARF. To mitigate some attack vectors introduced by this attack scenario, we deploy a complex tweak-key schedule. Due to the shortage of suitable 32-bit designs, we compare our design to various low-latency ciphers with different block sizes. Our hardware implementation shows competitive latency numbers.

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Publication Details

Journal
IACR Transactions on Symmetric Cryptology
Published
2025-12-17
DOI
https://doi.org/10.46586/tosc.v2025.i4.31-69
Primary Topic
Cryptographic Implementations and Security
Type
article
Field-Weighted Citation Impact
0.00

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article

BEANIE – A 32-bit Cipher for Cryptographic Mitigations Against Software Attacks

Samir Hodžić, Maria Eichlseder, Glen McConville, Marcel Medwed et al.
IACR Transactions on Symmetric Cryptology
Cryptographic Implementations and Security
article

BEANIE – A 32-bit Cipher for Cryptographic Mitigations Against Software Attacks

Samir Hodžić, Maria Eichlseder, Glen McConville, Marcel Medwed, Jan Hoogerbrugge, Marcel Nageler, Simon Gerhalter, Tobias Schneider, Artur Folwarczny, Ventzi Nikov
article en

Abstract

In modern CPU architectures, various security features to mitigate software attacks can be found. Examples of such features are logical isolation, memory tagging or shadow stacks. Basing such features on cryptographic isolation instead of logical checks can have many advantages such as lower memory overhead and more robustness against misconfiguration or low-cost physical attacks. The disadvantage of such an approach is however that the cipher that has to be introduced has a severe impact on the system performance, either in terms of additional cycles or a decrease of the maximum achievable frequency. Finally, as of today, there is no suitable low-latency cipher design available for encrypting 32-bit words as is common in microcontrollers. In this paper, we propose a 32-bit tweakable block cipher tailored to memory encryption for microcontroller units. We optimize this cipher for low latency, which we achieve by a careful selection of components for the round function and leveraging an attack scenario similar to the one used to analyze the cipher SCARF. To mitigate some attack vectors introduced by this attack scenario, we deploy a complex tweak-key schedule. Due to the shortage of suitable 32-bit designs, we compare our design to various low-latency ciphers with different block sizes. Our hardware implementation shows competitive latency numbers.

IACR Transactions on Symmetric CryptologyVol. 2025(4)
NXP (Netherlands) (NL), Graz University of Technology (AT), NXP (Belgium) (BE)
European Commission, Austrian Science Fund, Österreichische Forschungsförderungsgesellschaft
Openalex Percentile: Top 78%
Cryptographic Implementations and Security
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