Hardware/Software Partitioning Based on Area and Memory Metrics: Application to a Fuzzy Controller Algorithm for a DC Motor

In hardware/software (HW/SW) partitioning, the most commonly established objectives are execution time, power consumption, and hardware area. Surprisingly, memory usage, a critical resource in embedded systems, has received limited attention as a primary optimization objective. Moreover, the few studies that consider memory rarely provide an explicit, design-time estimation method. This work proposes a methodology for obtaining memory usage as a design metric, along with an objective function tailored to evaluate memory usage in systems-on-chip featuring a hard processor core and a Field-Programmable Gate Array suitable for a HW/SW partitioning problem. To validate the proposed methodology, HW/SW partitioning was carried out for a PD-type fuzzy control algorithm targeting a DC motor. The optimization problem was solved using the Non-dominated Sorting Genetic Algorithm II. The results demonstrate the feasibility and accuracy of the proposed approach, achieving more than 97.5% accuracy in predicting memory and hardware resource consumption. Additionally, the functional performance of the selected partition configuration was validated in real-time, where the tracking of different reference signals for the velocity of the motor was successfully achieved.