FPGA‐Based Quadrature Phase Shift Keying Modulator With Carrier Derived From Negative Impedance Converter Equation

The wireless communication infrastructure software‐defined radio (SDR) is nowadays essential due to the explosion of digital communication because of its high configurable hardware and software platforms. Several complex signal processing tasks are performed by SDR, and field programmable gate arrays (FPGAs) are the best solution to implement such tasks of SDR. Quadrature phase shift keying (QPSK) is widespread in numerous SDR systems for digital transmission. To generate QPSK signals, modulation approaches such as FPGA, VLSI, and CMOS are used. Analog oscillators are also used to generate carriers for digital transmission systems. Digital oscillators have been chosen to replace analog oscillators in FPGA‐based QPSK. Among the design techniques of digital oscillators, we can name the direct digital synthesis (DDS) and the CORDIC algorithm. The two techniques present some drawbacks at the level of memory storage, processing time, and latency. In this paper, we develop an FPGA‐based QPSK modulator with a digital oscillator using a numerical solver that utilizes a negative impedance converter (NIC) circuit. The proposed modulator is built and is able to generate the sine and cosine functions. Our proposed modulator is made of an NIC‐based digital solver, two multiplexers, three logical arithmetic operators, a flip‐flop, and a digital‐to‐analog converter. The implementation is performed on the IV‐EEP4CE115F29C7N chip of the DE2‐115 board described in the VHDL language with 64‐bit fixed‐point words according to IEEE 754 standards. After analysis, the NIC‐based modulator presents a signal‐to‐noise ratio (SNR) of 7.28, an error vector magnitude (EVM) of 49.65%, a bit error rate (BER) of 0.73 for a 4‐QAM and an SNR of 12.48, an EVM of 72.81%, and a BER of 0.46 for a 16‐QAM. At the experimental level, we have 1002 logic components, 119 registers, 0 memory bits, 0 integrated multipliers, and 153.57 mW of estimated power consumption. The proposed modulator consumes more resources than a direct digital frequency synthesis (DDFS)‐based modulator. However, despite the high power consumption, it features no embedded multipliers and no bit of memory used. The digital modulator we propose can be used in cases where low power consumption is required and the storage capacity is not desired, as demonstrated by experimental results.