Area efficient approximate multiplier based on novel 4:2 compressors and error correction logic

Multipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hardware resources, particularly in applications where that can tolerate minimal accuracy loss. Achieving higher multiplier performance typically requires a careful trade-off between hardware complexity and computational precision. One widely adopted method for designing approximate multipliers involves replacing exact compressors with their approximate counterparts, resulting in a trade-off with accuracy. This paper introduces novel approximate multiplier architectures that partition the computation into three distinct regions: accurate, approximate, and lower region. Partial product compression in the approximate region is carried out using the proposed two 4:2 compressors combined with conventional arithmetic circuits like half adder, full adder and OR logic, to produce the final product. The proposed compressors are developed by analyzing the input occurrence probability of all possible combinations with trade-off between hardware efficiency and computational accuracy. To further improve accuracy, an error correction logic is developed to compensate for inaccuracies in specific input scenarios. Several benchmark error metrics and hardware synthesis using a 32-nm CMOS technology are evaluated for the proposed designs through simulations. Notably, the results of the proposed approximate multipliers shows an average improvements of 70.6% in accuracy, 60.4% in Energy-Delay Product, 30.9% in Power-Delay Product, and 41.6% in delay, outperforming all existing designs considered for comparison. Furthermore, real-time image multiplication experiments were performed using multiple benchmark image datasets, and the output quality was evaluated through the Similarity Index Metric (SSIM) and Peak Signal-to-Noise Ratio (PSNR). In addition, detailed error and heat-map visual analyses were conducted to examine the spatial distribution and intensity of computational errors across pixels. The results demonstrate that the proposed multiplier consistently achieves higher SSIM and PSNR values, along with significantly reduced error concentrations, outperforming existing approximate multiplier designs.