End-to-End Quantization Co-Design for MHz GaN Converters using Dither and Sigma-Delta Modulation

We study end-to-end quantization in digitally controlled MHz-range GaN DC–DC converters, spanning the analog-to-digital converter (ADC), fixed-point controller, and digital pulse-width modulator (DPWM). A simulation framework sweeps ADC and DPWM resolutions across buck, boost, and inverting buck–boost converters at 1, 5, and 10 MHz, reporting regulation bias, output ripple, and limit-cycle occurrence. A simple metric ρ compares the DPWM step (mapped to V_out) to the ADC least-significant bit and accurately predicts the onset of limit cycles: designs with ρ≥1 avoid limit cycles in all surveyed cases. The results yield practical rules: boost and buck–boost require finer DPWM than buck due to larger ∂V/∂D; dithering and first-order sigma–delta (ΣΔ) modulation provide roughly one to two effective DPWM bits at 1 MHz; and increasing switching frequency tightens timing margins but can be offset by modest DPWM resolution or reduced digital delay. Validation includes analytic–simulated slope agreement, ρ–versus–limit-cycle slices, and robustness to parasitic spreads, ADC noise, and jitter. These findings provide concise, quantitative guidance for selecting ADC and DPWM resolutions to meet ≤10–20 mV ripple targets without limit cycles in MHz GaN converters.