FPGA-accelerated convolutional method for peanut pod appearance recognition

Peanuts are a major economic crop where post-harvest visual grading remains largely manual, slow, and error-prone. This paper presents a peanut pod appearance recognition network (PPRNET), a lightweight 12-layer Convolutional Neural Network (CNN) accelerated on a low-cost Field-Programmable Gate Array (FPGA). The network combines depthwise separable convolutions with structured pruning and post-training quantization, yielding 382,918 parameters (1.46 MB) and 0.09 floating-point operations (GFLOPs). The accelerator uses an NC4HW4 memory layout to enhance data processing. HLS techniques such as UNROLL, PIPELINE, ARRAY_PARTITION, and DATAFLOW, along with ping-pong buffering, help speed up computation and memory access by allowing parallel execution. The deployed system processes one image in 13 ms and attains 99.16 % classification accuracy on the peanut pod dataset. Relative to MobileNetV2 (2.23 M parameters, 0.17 GFLOPs, 99.58 % accuracy), PPRNET reduces parameters by 82.84 % and GFLOPs by 47.06 % with only a 0.42-percentage-point accuracy drop; compared with MobileNetV3-Small, it uses just 25.13 % of the parameters. These results support the FPGA choice: fine-grained parallelism and dataflow pipelining provide deterministic low latency and high energy efficiency under strict memory/compute budgets. Compared with CPU-class boards such as Raspberry Pi and embedded Graphics Processing Unit (GPU) platforms such as Jetson Nano, the ZYNQ-7020 achieves faster inference at lower cost and better portability. Overall, algorithm–hardware co-design enables accurate, efficient, and field-ready on-site grading for peanut pod classification. • A CNN, PPRNET, was designed for peanut pod appearance recognition. • An FPGA circuit was designed to accelerate the CNN and successfully deployed. • Impacts of architecture, convolution, input size, and memory layout were analyzed.