Modulation and Capacitor Balancing of a Single-Phase Two-Series-Connected Diode-Clamped PWM Inverter With Seven-Level Input

This paper proposes a two-series-connected seven-level diode-clamped PWM inverter that realize a true seven-level dc link from a single high-voltage (HV) source using six series capacitors —without auxiliary boosting network or multiple isolated sources. To address the long-standing challenge of capacitor-voltage imbalance in high-level diode-clamped structures, a dual inter- and intra-leg balancing strategy is developed from an analytical model of the dc-link voltage variation mechanism governed by the combined action of intermediate/neutral-vector duty cycles and phase currents. Simulation studies demonstrate steady-state performance, including line-voltage total harmonic distortion (THD) of 25–30% and current THD of 0.45–0.75% at modulation index <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i>=1 across SPWM and MNRV-DPWM variants, switching frequencies of 1.97–3.95 kHz, and clearly distinguished loss profiles depending on the clamping pattern. Simulated efficiencies fall within 92–97% across the tested PWM strategies, with clear distinctions in the associated conduction and switching loss profiles. The dc-blocking-capacitor ripple remains well-bounded (≈26 V, or 13% of its average voltage), confirming proper capacitor sizing. A hardware prototype further confirms the effectiveness of the proposed control and the inherent balancing capability of the topology. The measured current THD (≈1.7–2.0%) is in close agreement with the simulated spectra, and the measured voltage THD (≈32–39%) at a power factor of 0.9 and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i>=1 follows the predicted line-to-line output behavior. These results establish the presented topology and control as an efficient, reliable, and deployment-ready option for single-source, HV, high-power applications.