Opcode Analysis of Real Encryption-Based Microarchitectural Attacks Using gem5

Modern processors employ performance-enhancing features such as speculative execution and multi-level caching, but these same mechanisms can inadvertently expose sensitive information through microarchitectural side channels. This work introduces a precise, simulation-driven framework for identifying how individual cryptographic instructions contribute to such leakage. We present a systematic opcode-level analysis of AES-NI instructions (including AESENC, AESDEC, and AESKEY-GENASSIST) and quantify their susceptibility to Flush+Reload attacks using cycle-accurate gem5 simulations. Our results reveal distinct microarchitectural footprints for each opcode: AES-ENC exhibits measurable timing and cache activity arising from state and round-key memory operations surrounding the hardware-implemented transform, while AESKEYGENASSIST incurs the highest latency due to iterative key-schedule computations. Control-flow instructions such as JNE further amplify leakage by introducing branch mispredictions. A key outcome of this study is the close match between simulation and physical measurements achieving 89% key recovery in gem5 versus 96% on an Intel CPU, demonstrating that gem5 reliably captures the dominant leakage behaviors despite abstracted hardware details. We additionally show that smaller last-level caches intensify leakage by concentrating access patterns, whereas larger caches reduce, but do not eliminate the exposure. Overall, this work provides actionable insights for designing hardened cryptographic software and developing future detection mechanisms, and highlights the value of architectural simulation for early-stage security assessment.