HPC Workload Analysis Using Distributed Cross-ISA Binary Instrumentation

Developing distributed High Performance Computing (HPC) applications is challenging, with complex interactions between application, runtime environment, processing cores, and network to obtain the highest performance that a given distributed computing system can provide. HPC systems are evolving at a fast pace, so applications must often be ported. Generally, developers natively run their applications on current machines and extrapolate the performances on future ones. However, modern and future HPC machines contain multiple nodes, each with multiple general-purpose processor cores, possibly with an Instruction Set Architecture (ISA) different from the previous generations, as well as new domain-specific accelerators, so simple extrapolations may not be accurate. Instead, we propose an automated approach to execute and nonintrusively characterize distributed HPC applications on a QEMU-based, cross-ISA, distributed simulation platform. As part of this automated approach, we propose a QEMU plugin to extract metrics at runtime during the execution of distributed applications. The approach is demonstrated on a RISC-V-based distributed multinode architecture. It achieves an average speedup of almost <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.5 \times$</tex> on a single host machine with 16 virtual nodes in comparison with a single node. Using QEMU plugins for collecting Message Passing Interface (MPI) runtime metrics slows the simulation by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.62 \times$</tex> in average, but overall, our approach remains much faster than other simulation platforms.

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Published
2025-11-26
DOI
https://doi.org/10.1109/dcis67520.2025.11281913
Primary Topic
Parallel Computing and Optimization Techniques
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article
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article

HPC Workload Analysis Using Distributed Cross-ISA Binary Instrumentation

César Fuguet, Christian Fabre, Frédéric Pétrot, Eduardo Tomasi
Parallel Computing and Optimization Techniques
article

HPC Workload Analysis Using Distributed Cross-ISA Binary Instrumentation

César Fuguet, Christian Fabre, Frédéric Pétrot, Eduardo Tomasi
article en

Abstract

Developing distributed High Performance Computing (HPC) applications is challenging, with complex interactions between application, runtime environment, processing cores, and network to obtain the highest performance that a given distributed computing system can provide. HPC systems are evolving at a fast pace, so applications must often be ported. Generally, developers natively run their applications on current machines and extrapolate the performances on future ones. However, modern and future HPC machines contain multiple nodes, each with multiple general-purpose processor cores, possibly with an Instruction Set Architecture (ISA) different from the previous generations, as well as new domain-specific accelerators, so simple extrapolations may not be accurate. Instead, we propose an automated approach to execute and nonintrusively characterize distributed HPC applications on a QEMU-based, cross-ISA, distributed simulation platform. As part of this automated approach, we propose a QEMU plugin to extract metrics at runtime during the execution of distributed applications. The approach is demonstrated on a RISC-V-based distributed multinode architecture. It achieves an average speedup of almost <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3.5 \times$</tex> on a single host machine with 16 virtual nodes in comparison with a single node. Using QEMU plugins for collecting Message Passing Interface (MPI) runtime metrics slows the simulation by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.62 \times$</tex> in average, but overall, our approach remains much faster than other simulation platforms.

Institut polytechnique de Grenoble (FR), Centre National de la Recherche Scientifique (FR), Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR), CEA Grenoble (FR), Techniques of Informatics and Microelectronics for Integrated Systems Architecture (FR), Centre Inria de l'Université Grenoble Alpes (FR), Université Grenoble Alpes (FR)
Openalex Percentile: Top 56%
Parallel Computing and Optimization Techniques
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