Protected Phase Gate for the 0- <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" display="inline"> <mml:mi>π</mml:mi> </mml:math> Qubit using its Internal Modes

Protected superconducting qubits such as the 0- <a:math xmlns:a="http://www.w3.org/1998/Math/MathML" display="inline"> <a:mi>π</a:mi> </a:math> qubit promise to substantially reduce physical error rates. However, a key challenge in the field is designing gates for these qubits that do not compromise their protection or become infeasibly slow as the protection of the qubit is improved. In this work we propose a protected phase gate that is compatible with the protected regime of the 0- <c:math xmlns:c="http://www.w3.org/1998/Math/MathML" display="inline"> <c:mi>π</c:mi> </c:math> qubit and does not suffer from spurious coupling to additional circuit modes. Our gate utilizes an internal mode of the circuit as an ancilla and is achieved by varying the qubit-ancilla coupling via a tunable Josephson element. Through numerical simulations, we study how the gate error scales with the circuit parameters of the 0- <e:math xmlns:e="http://www.w3.org/1998/Math/MathML" display="inline"> <e:mi>π</e:mi> </e:math> qubit and the tunable Josephson element that enacts the gate. Ultimately, we find that a protected gate with the 0- <g:math xmlns:g="http://www.w3.org/1998/Math/MathML" display="inline"> <g:mi>π</g:mi> </g:math> qubit is possible with near-term circuit parameters. Our work opens up the possibility of performing protected gates on protected superconducting qubits, which may significantly reduce hardware overheads for quantum computation.