Compact and efficient realization of fractional-order filter using admittance equalization-based fractional device

Abstract This paper proposes a novel fractance device (FD) based on simple R-C pairs for realizing fractional-order analog filters. Unlike conventional R-C ladder network-based FDs, which are complex and bulky, the proposed design employs only two passive components. This simplification results in lower cost, compact hardware, and improved power efficiency. The proposed FD is implemented in a VDTA-based fractional-order universal filter to evaluate its performance. The accuracy and validity of the proposed design are verified through SPICE and MATLAB simulations. Further, Monte Carlo analysis confirms the robustness and stability of the proposed circuit under parameter variations. The novelty of this work lies in its minimal-component realization of fractance behavior without compromising performance. The proposed approach supports SDG 7 (Affordable and Clean Energy) and SDG 9 (Industry, Innovation, and Infrastructure), advancing energy-efficient and innovative solutions for modern communication and signal processing systems.