Opto-electronic simulation of silicon waveguide integrated single photon avalanche diodes

Single-photon avalanche diodes (SPADs) integrated into photonic integrated circuits (PICs) can offer a promising alternative to cryogenic superconducting detectors, combining CMOS compatibility with room-temperature operation. A comprehensive optoelectronic multiphysics simulation framework to model waveguide integrated SPADs is shown here. Based on imec's isipp50G technology, simulated devices show the potential of peak photon detection efficiencies (PDE) above 75% at 600 nm, when coupled with a SiN signal waveguide. This work establishes a scalable methodology for design technology co-optimization (DTCO) of SPADs for integrated photonics and identifies critical pathways towards performance improvements, mainly in dark count rate (DCR) reduction, paving the way for their full optimization and integration into quantum photonic circuits.