Simulation of the Effects of the Pillar Configurations on 1.2 kV 4H-SiC Superjunction DMOSFET

4H-SiC has been studied and applied in power semiconductor devices due to its wider band gap and higher thermal conductivity than those of Si and hence has great potential for power devices operating at high powers and high temperatures. The introduction of the superjunction (SJ) structure for the power MOSFETs enables further reduction in the ON resistance while maintaining the breakdown voltage. In this work, we examined the dc and ac performance of the 1.2 kV 4H-SiC SJ double-implanted MOSFET (DMOSFET) with different configurations of pillars by the Atlas device simulator. The simulation results suggest the step-shape SJ DMOSFET can further reduce the specific ON resistance and the gate-drain capacitance while maintaining the breakdown voltage compared with the optimized conventional SJ DMOSFET. In addition, that the multi-pillar SJ DMOSFET demonstrates better performance than that of the optimized conventional SJ DMOSFET was also verified in this work.