A 5 MS/s 27.2 μW cryo-CMOS SAR ADC for space telescopes using energy-scalable comparator

This paper proposes an energy-scalable comparator using the floating-inverter amplifier (FIA). The proposed comparator features advanced gm/ID characteristic of the FIA-based comparator while simultaneously exhibiting the energy-scalability with respect to input difference, a feature typically found in voltage-controlled oscillator (VCO)-based comparators. Therefore, the proposed comparator can save energy consumption while maintaining the same fast comparison speed as conventional FIA-based comparators. The comparator was implemented in an 11-bit cryo-CMOS successive approximation register analog-to-digital converter (SAR ADC) for space telescopes in 65-nm process. It guarantees robust operation in both room and cryogenic temperatures. At the cryogenic temperature, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 67.2 dB at a 5 MS/s sampling rate.