Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage

Timing closure is a critical but effort-taking task in VLSI designs. In this paper, we investigate timing models and their associated optimization techniques suitable for integration into early design process. For accurate timing analysis at placement stage, an innovative timing prediction model that can be transformed into a derivable function is proposed, serving as a replacement for the conventional Elmore delay. One significant advantage of derivable timing models is their ability to be formulated as mathematical functions. This enables the derivation of gradients, which can be explored as direct timing optimization guidance during design process. Therefore, we further present a timing optimization method through model integration into iterative placement process. Experimental results demonstrate that our derivable timing model provides accurate prediction performance. Additionally, when integrated into the placement stage, it outperforms the use of Elmore delay and non-derivable models, achieving 12% ∼ 24% smaller Total Negative Slack (TNS) and Worst Negative Slack (WNS), with an average wirelength reduction of 1% ∼ 5%.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2025-12-08
DOI
https://doi.org/10.1145/3780100
Primary Topic
VLSI and FPGA Design Techniques
Type
article
Field-Weighted Citation Impact
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article

Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage

Yibo Lin, Peiyu Liao, Bei Yu, Yao Wang et al.
ACM Transactions on Design Automation of Electronic Systems
VLSI and FPGA Design Techniques
article

Efficient Timing Prediction and Optimization Using Derivable Gradient Boosting Machine Model at Placement Stage

Yibo Lin, Peiyu Liao, Bei Yu, Yao Wang, Chang Liu, Yang Guo, Xu He, Chenjing Yang, Rongchun Zhao, Yushan Wang
article en

Abstract

Timing closure is a critical but effort-taking task in VLSI designs. In this paper, we investigate timing models and their associated optimization techniques suitable for integration into early design process. For accurate timing analysis at placement stage, an innovative timing prediction model that can be transformed into a derivable function is proposed, serving as a replacement for the conventional Elmore delay. One significant advantage of derivable timing models is their ability to be formulated as mathematical functions. This enables the derivation of gradients, which can be explored as direct timing optimization guidance during design process. Therefore, we further present a timing optimization method through model integration into iterative placement process. Experimental results demonstrate that our derivable timing model provides accurate prediction performance. Additionally, when integrated into the placement stage, it outperforms the use of Elmore delay and non-derivable models, achieving 12% ∼ 24% smaller Total Negative Slack (TNS) and Worst Negative Slack (WNS), with an average wirelength reduction of 1% ∼ 5%.

ACM Transactions on Design Automation of Electronic Systems
National Defense University (US), Hunan University (CN), National University of Defense Technology (CN), Chinese University of Hong Kong (HK), Changsha University (CN), Peking University (CN), Hunan University of Science and Engineering (CN), Milli Savunma Üniversitesi (TR)
Openalex Percentile: Top 61%
VLSI and FPGA Design Techniques
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