Hybrid-gate MoS2 2T0C DRAM for low-power multi-bit storage with high linearity

With the increasing demand for high-performance computing, 2T0C DRAM has been extensively studied for its high integration density, low power consumption and non-destructive readout. Two-dimensional (2D) semiconductors, with ultra-low leakage current, improve the retention characteristics but face limitations in conventional 2D-based 2T0C cells: the subthreshold operation of positive-threshold transistors at low write voltages reduces read current, introduces nonlinearity, and degrades robustness, and thus requires higher write voltages and increased power consumption. To address this, we propose a hybrid-gate MoS<sub>2</sub> 2T0C DRAM, where a low-leakage Au-gate transistor serves as the write node and a depletion-mode Al-gate transistor functions as the readout node. The device achieves >100 s retention time and reduces the minimum write voltage to 0.2 V, enabling distinguishable 3-bit storage. Furthermore, a 32 × 32 MoS<sub>2</sub> 2T0C DRAM circuit demonstrates image storage and readout capabilities with <5% bit error rate after 600 s, highlighting its potential for future high-density, low-power memory applications.

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Publication Details

Journal
National Science Review
Published
2025-12-05
DOI
https://doi.org/10.1093/nsr/nwaf555
Primary Topic
Ferroelectric and Negative Capacitance Devices
Type
article
Field-Weighted Citation Impact
0.00

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article

Hybrid-gate MoS2 2T0C DRAM for low-power multi-bit storage with high linearity

Yufei Song, Yuxuan Zhu, Zhejia Zhang, Zhengjie Sun et al.
National Science Review
Ferroelectric and Negative Capacitance Devices
article

Hybrid-gate MoS2 2T0C DRAM for low-power multi-bit storage with high linearity

Yufei Song, Yuxuan Zhu, Zhejia Zhang, Zhengjie Sun, Jinshu Zhang, Xinliu He, Peng Zhou, Haojie Chen, Qihao Chen, Xiangqi Dong, Wenzhong Bao, Saifei Gou, Mingrui Ao, Huihui Li, Xia Yin, Mingyuan Liu, Wang Yin, Yuchen Tian, Yang Liu, Yan Hu, Qicheng Sun, Hao Meng, Yang Chen, Jieya Shang
article en

Abstract

With the increasing demand for high-performance computing, 2T0C DRAM has been extensively studied for its high integration density, low power consumption and non-destructive readout. Two-dimensional (2D) semiconductors, with ultra-low leakage current, improve the retention characteristics but face limitations in conventional 2D-based 2T0C cells: the subthreshold operation of positive-threshold transistors at low write voltages reduces read current, introduces nonlinearity, and degrades robustness, and thus requires higher write voltages and increased power consumption. To address this, we propose a hybrid-gate MoS<sub>2</sub> 2T0C DRAM, where a low-leakage Au-gate transistor serves as the write node and a depletion-mode Al-gate transistor functions as the readout node. The device achieves >100 s retention time and reduces the minimum write voltage to 0.2 V, enabling distinguishable 3-bit storage. Furthermore, a 32 × 32 MoS<sub>2</sub> 2T0C DRAM circuit demonstrates image storage and readout capabilities with <5% bit error rate after 600 s, highlighting its potential for future high-density, low-power memory applications.

National Science ReviewVol. 13(2)
Shaoxing University (CN), Hefei University (CN), Shanghai Customs College (CN), Shaoxing City Women and Children Hospital (CN), Shanghai Fudan Microelectronics (China) (CN), Shanghai Institute of Technology (CN)
National Natural Science Foundation of China, Fudan University, Shanghai Municipal Education Commission, Science and Technology Commission of Shanghai Municipality, National Key Research and Development Program of China
Openalex Percentile: Top 61%
Ferroelectric and Negative Capacitance Devices
DOIOpen Access PDFOpenAlex
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