Mechanism of void growth in electroless copper plating layer of microvias in high-density interconnect packaging substrates

Abstract Voids in electroless copper (Cu) plating layers critically influence the reliability of microvias in high-density interconnect (HDI) packaging substrates. This study investigates void formation mechanisms by fabricating multilayered Cu structures that simulate microvia interconnections and performing electroless Cu plating under controlled nickel (Ni) ion concentrations and bath temperatures. Void morphology and distribution are analyzed using transmission electron microscopy (TEM) and quantitative image analysis. The results reveal that increased Ni content and elevated bath temperatures accelerate the plating rate, thereby promoting void formation at the initial stage of deposition. Theoretical analysis suggests that this behavior is driven by surface cohesion forces acting on nascent voids. A void growth mechanism is proposed, wherein voids predominantly originate within the initial Cu layer due to localized hydrogen accumulation near palladium (Pd) catalysts. In contrast, subsequent layers—deposited after Pd sites are buried—exhibit reduced maximum (max.) void sizes and lower void fractions. These findings provide mechanistic insight into void evolution in electroless Cu layers and underscore the critical role of Ni content and bath temperature in enhancing HDI packaging substrate reliability.