A 28 Gbps High‐Compensation, Low‐Power CTLE Design for SerDes in 28‐nm CMOS Technology

ABSTRACT As data volume and transmission rates through signals escalate, high‐frequency signals experience significant attenuation owing to the channel's nonideal characteristics. Consequently, equalization circuits are imperative to mitigate channel loss. This manuscript introduces a cascaded approach that integrates an attenuation circuit (adaptive thresholding technique [ATT]) with a multistage continuous‐time linear equalizer (CTLE) featuring a negative impedance structure to balance the signal. The signal is subjected to prefiltering and common‐mode adjustment by the ATT circuit, concurrently attenuating low‐frequency components. The multistage CTLE circuit, incorporating a negative impedance structure, executes signal equalization, efficiently compensating for channel loss at elevated data rates. Simulation outcomes reveal that the proposed equalizer is capable of offsetting a 27‐dB channel loss at a data rate of 28 Gbps, achieving a gain of −15.38 dB at 10 MHz and 17.7 1dB at 14 GHz, with a power consumption of 57.76 mW. The equalizer's figure of merit regarding power consumption rates at 2.06 pJ/bit and 0.076 pJ/bit/dB, and it occupies a layout area of 0.012 mm 2 . In comparison with state‐of‐the‐art equalizer designs, this equalizer exhibits superior power efficiency while preserving a high degree of compensation capability.