The impact of Back-Gate biasing and layout on temperature sensitivity of transistors in FD-SOI CMOS technology

FD-SOI technology offers degrees of freedom in analog and digital circuit design through back-gate biasing. This work investigates the influence of back-gate voltage and layout on the temperature sensitivity of transistors this, through both simulation and measurement. A temperature-compensated voltage reference, from a previous work of ours, is employed as a test vehicle. We compare three layout strategies to evaluate spatial effects on temperature drift. The measurement campaign, conducted using a dedicated datalogger and temperature-controlled setup, confirms simulation about temperature-induced variations. The results underline the importance of careful back-gate management in FD-SOI for robust design.