One-Step Dead Time Correction with Fault Protection Using Parasitic Components

This paper presents a one-step dead time correction method based on real-time detection of gate-source voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{G}\mathrm{S}})$</tex> and common source inductance voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\mathrm{L}_{\mathrm{s}}})$</tex>, eliminating the need for additional high-voltage (HV) components and propagation delay. The proposed approach determines near-optimal dead time in a single switching cycle and integrates fault protection to enhance reliability and efficiency with minimal computation overhead. The method is experimentally validated on a 48V-12V synchronous buck converter at 100kHz. The results demonstrate a 2% - 3% absolute efficiency improvement and a 13.5% - 34.6 % relative power loss reduction compared to a fixed 500ns dead time setting over a wide load current range.

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Publication Details

Published
2025-10-19
DOI
https://doi.org/10.1109/ecce58356.2025.11259617
Primary Topic
Low-power high-performance VLSI design
Type
article
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article

One-Step Dead Time Correction with Fault Protection Using Parasitic Components

Joachim Joos, Valentijn De Smedt, Hongming Zhao
Low-power high-performance VLSI design
article

One-Step Dead Time Correction with Fault Protection Using Parasitic Components

Joachim Joos, Valentijn De Smedt, Hongming Zhao
article en

Abstract

This paper presents a one-step dead time correction method based on real-time detection of gate-source voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{V}_{\mathrm{G}\mathrm{S}})$</tex> and common source inductance voltage <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{\mathrm{L}_{\mathrm{s}}})$</tex>, eliminating the need for additional high-voltage (HV) components and propagation delay. The proposed approach determines near-optimal dead time in a single switching cycle and integrates fault protection to enhance reliability and efficiency with minimal computation overhead. The method is experimentally validated on a 48V-12V synchronous buck converter at 100kHz. The results demonstrate a 2% - 3% absolute efficiency improvement and a 13.5% - 34.6 % relative power loss reduction compared to a fixed 500ns dead time setting over a wide load current range.

Robert Bosch (Germany) (DE), KU Leuven (BE)
Openalex Percentile: Top 62%
Low-power high-performance VLSI design
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