N-Phase Interleaved Power Stage with Asynchronous Delta-Sigma Modulator for Dynamic Converters

This paper proposes a modulation strategy for interleaved power converters using asynchronous delta-sigma modulation (ADSM). While ADSM offers advantageous spread-spectrum characteristics and noise shaping, its variable switching frequency poses challenges for interleaved operation. We propose a master-slave synchronization architecture based on a phase-locked loop (PLL), where each ADSM modulator is treated as a controlled oscillator. By adjusting the ADMS tunable delay, the PLL maintains fixed phase offsets across an arbitrary number of interleaved legs, despite variable switching frequencies. The approach is validated by deriving system equations, behavioral simulations, and experimental measurements on a three-leg, 30 A, 400 V GaN-based power stage. A digital emulation of the continuous-time modulator was implemented on an FPGA, demonstrating practical feasibility. Results confirm effective phase locking within ±15°, reduced output ripple by 67%, and enhanced EMI performance by 5.4 dB.

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Publication Details

Published
2025-10-19
DOI
https://doi.org/10.1109/ecce58356.2025.11259673
Primary Topic
Electromagnetic Compatibility and Noise Suppression
Type
article
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article

N-Phase Interleaved Power Stage with Asynchronous Delta-Sigma Modulator for Dynamic Converters

Gernot Schullerus, Eckhard Hennig, E. Sönmez, Philipp Czerwenka et al.
Electromagnetic Compatibility and Noise Suppression
article

N-Phase Interleaved Power Stage with Asynchronous Delta-Sigma Modulator for Dynamic Converters

Gernot Schullerus, Eckhard Hennig, E. Sönmez, Philipp Czerwenka, J. Maier
article en

Abstract

This paper proposes a modulation strategy for interleaved power converters using asynchronous delta-sigma modulation (ADSM). While ADSM offers advantageous spread-spectrum characteristics and noise shaping, its variable switching frequency poses challenges for interleaved operation. We propose a master-slave synchronization architecture based on a phase-locked loop (PLL), where each ADSM modulator is treated as a controlled oscillator. By adjusting the ADMS tunable delay, the PLL maintains fixed phase offsets across an arbitrary number of interleaved legs, despite variable switching frequencies. The approach is validated by deriving system equations, behavioral simulations, and experimental measurements on a three-leg, 30 A, 400 V GaN-based power stage. A digital emulation of the continuous-time modulator was implemented on an FPGA, demonstrating practical feasibility. Results confirm effective phase locking within ±15°, reduced output ripple by 67%, and enhanced EMI performance by 5.4 dB.

Reutlingen University (DE)
Openalex Percentile: Top 62%
Electromagnetic Compatibility and Noise Suppression
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