Analysis of the Desaturation Circuit Behaviour Under Paralleled GaN Devices Including the Effects of Parasitic Parameters

The paper introduces a desaturation-based short-circuit protection scheme, optimized for GaN devices in parallel configuration and subject to parasitic effects. When connecting GaN devices in parallel, a careful design is essential to limit mismatches in the parasitic inductances and capacitances in the power and drive paths among the different legs in parallel. Even when well balanced, parasitic parameters generate oscillations that are responsible for false alarms or delays in short-circuit detection. The paper analyzes in detail the origins of these instabilities and introduces design guidelines to mitigate their impact. A simulation campaign investigates a half-bridge circuit composed of four paralleled GaN devices. Key design challenges are identified, and targeted recommendations are provided to improve robustness and ensure timely fault detection. The results demonstrate that, with proper design, the desaturation technique can ensure reliable short-circuit detection. The detection time achieved at 400V DC is 150ns with a total protection response time of 250ns.

Authors

Institutions

Publication Details

Published
2025-10-19
DOI
https://doi.org/10.1109/ecce58356.2025.11259650
Primary Topic
Silicon Carbide Semiconductor Technologies
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Analysis of the Desaturation Circuit Behaviour Under Paralleled GaN Devices Including the Effects of Parasitic Parameters

Giulio De Donato, Fabio Giulii Capponi, Guido Rubino, Rahul Kumar
Silicon Carbide Semiconductor Technologies
article

Analysis of the Desaturation Circuit Behaviour Under Paralleled GaN Devices Including the Effects of Parasitic Parameters

Giulio De Donato, Fabio Giulii Capponi, Guido Rubino, Rahul Kumar
article en

Abstract

The paper introduces a desaturation-based short-circuit protection scheme, optimized for GaN devices in parallel configuration and subject to parasitic effects. When connecting GaN devices in parallel, a careful design is essential to limit mismatches in the parasitic inductances and capacitances in the power and drive paths among the different legs in parallel. Even when well balanced, parasitic parameters generate oscillations that are responsible for false alarms or delays in short-circuit detection. The paper analyzes in detail the origins of these instabilities and introduces design guidelines to mitigate their impact. A simulation campaign investigates a half-bridge circuit composed of four paralleled GaN devices. Key design challenges are identified, and targeted recommendations are provided to improve robustness and ensure timely fault detection. The results demonstrate that, with proper design, the desaturation technique can ensure reliable short-circuit detection. The detection time achieved at 400V DC is 150ns with a total protection response time of 250ns.

Sapienza University of Rome (IT)
Openalex Percentile: Top 62%
Silicon Carbide Semiconductor Technologies
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

Analysis of the Desaturation Circuit Behaviour Under Paralleled GaN Devices Including the Effects of Parasitic Parameters — Giulio De Donato, Fabio Giulii Capponi, et al. · (2025) | TGRS Research Map | TGRS