Comparative Study on Device Type Configurations of 2T0C DRAM for Compute-in-Memory Applications

In this article, we systematically analyze the electrical characteristics of 2T0C DRAM unit cells for compute-in-memory (CIM) applications, focusing on the on/off current ratio, coupling effects, and retention time, with respect to the NN (NMOS-NMOS), NP (NMOS-PMOS), PN (PMOS-NMOS), and PP (PMOS-PMOS) device types. We designed 65 nm CMOS-based 2T0C DRAM unit cells using Sentaurus 3D TCAD simulation, while keeping the physical parameters and doping concentrations of the NMOS and PMOS transistors identical to impartially compare their electrical characteristics. As a result, the NP- and PN-type 2T0C DRAM cells exhibited much shorter retention times for data ‘0’ (<0.55 ns) and smaller on/off current ratios (<4.36) than the NN- and PP-type cells, clearly indicating that the NP- and PN-type cells are not favorable for CIM applications. Furthermore, we investigated the cause of the storage node voltage fluctuation immediately after a read pulse using the equivalent RC models of the NN- and PP-type cells. The origin of this fluctuation is attributed to three factors: the coupling effects between the storage node and the read transistor, the drain current in the read transistor, and the subthreshold leakage current in the write transistor.