Performance Evaluation of Digital Multipliers for Application in Neural Network Accelerators

This paper presents a performance analysis of three digital multiplier architectures—array, Wallace without carry-look-ahead (CLA), and Wallace with CLA logic—targeted for neural network (NN) accelerators. Simulations were performed using an IHP's 130 nm CMOS standard cell library in Cadence Spectre, focusing on propagation delay and power consumption across different supply voltages, temperatures and transistor dimensions. The Power Delay Product (PDP) was used to evaluate overall efficiency. Results show that the Wallace multiplier without CLA logic and the smallest cells offers the best trade-off in terms of delay and power, making it a strong candidate for low-power, high-performance applications.