Computational Analysis of Unipolar Stacked Switched Capacitor Architecture for Active Power Decoupling in Single-Phase Systems

Computational analysis using PSpice has become an indispensable tool for evaluating power electronics circuits, as it allows accurate simulation of transient effects, ripple, and component dynamics, enabling reliable assessment of complex topologies before physical implementation. In single-phase systems, electrolytic components are commonly used due to their high energy density, which helps mitigate low-frequency ripple caused by power oscillations between the DC and AC sides. However, these components have a limited lifespan, which compromises the system’s long-term reliability. This work proposes and evaluates the Stacked Switched Capacitor (SSC) topology as a power decoupling technique, implemented within a 200 W Cuk converter. The proposed SSC design enables a substantial reduction in required capacitance, replacing a conventional 600 μF capacitor with only three 36 μF capacitors, while maintaining voltage stability and output power performance. Simulation results show a high efficiency of 94% and a DC-link energy of 0.992 J, confirming the SSC’s ability to effectively mitigate voltage ripple at twice the grid angular frequency (2ω, rad/s) without compromising system durability. Comparative analysis with conventional decoupling strategies demonstrates that the SSC topology offers a compact, efficient, and reliable alternative, reducing the number of required passive components and switching devices. These results provide a strong basis for further exploration of SSC-based designs in space- and cost-constrained single-phase DC-AC applications.