Partitioning Cryogenic Integrated Electronics for Scalable Spin Qubit Operation

A systematic investigation of currently implemented cryogenic electronics for controlling and reading out spin qubits using complementary metal-oxide semiconductor (CMOS) technology is done. Scalability is the primary focus in developing these circuits, as enabling universal quantum computing requires increasing the number of qubits by several orders of magnitude. Low power dissipation is a main quality benchmark for cryogenic circuits that is being optimized. Next to that, the possibility of connecting multiple control signals to each qubit is a challenge for large qubit numbers. Depending on the placement of the electronics, different power budgets and connectivity options are available. These characteristics are used to discuss medium and long-term use-cases for existing designs and what future concepts and developments might be possible or necessary for full scalability on the example of spin qubit operation electronics.