Process Optimization for Metal-Contact Etching in 3D Integration Devices

This study investigates a metal-contact etching process that differs from conventional device contact etching by focusing on the film-stack configuration and the associated super-contact etching characteristics. Because metal-contact etching is closely linked to both physical profiles and electrical performance, evaluating a single parameter provides limited insight; thus, the physical profile characteristics of metal-contact etching and 3D-integrated super-contacts were comprehensively examined. In the first-step etch, the target depth in the wafer left region was approximately 2365 Å, and the bottom surface exhibited a desirable rounded profile. Following the removal of liner TEOS and nitride, the stopping margin was evaluated under three conditions: (1) metal-contact etching with a ~22 s target reduction, (2) a CMOS image-sensor baseline incorporating an interlayer-dielectric-reduction scheme, and (3) a high-selectivity condition achieved by increasing the C₅F₈/O₂ ratio with a reduced etch target. Under all three conditions, the bit-line contact (BLC) nitride experienced punch-through. To address this limitation, a three-step etch sequence was implemented, in which the first two steps achieved the required etch depth and the final step utilized a high-selectivity over-etch to secure a sufficient stopping margin. This approach demonstrated robust process windows, favorable CD control, and reliable nitride stopping performance, thereby establishing a practical methodology for stable super-contact etching in advanced 3D-integrated logic applications.