Coefficient Quantization and Enhanced Spectral Interpolation for Resource-Constrained Doppler Processing on FPGA

Accurate Doppler frequency detection is fundamental to radar systems for determining target velocity, yet a persistent trade-off exists between estimation accuracy and the computational resources required for real-time implementation, particularly on hard-ware-limited platforms like FPGAs. This study presents a novel filter bank architecture designed to resolve this conflict by employing two key methodological innovations: the strategic optimization of filter coefficient bit-width to minimize hardware resource consumption, and the development of an enhanced two-stage frequency estimation algorithm that interpolates the target Doppler shift from the outputs of adjacent filters. Simulation results and hardware implementation on a Xilinx Artix-7 FPGA demonstrate that the proposed design maintains high detection accuracy, with a stopband attenuation exceeding 50 dB and less than 0.05 dB passband deviation and reliably identifies multiple targets in low signal-to-noise ratio (SNR) environments of -20 dB, while concurrently reducing DSP block utilization by 40%. We conclude that this architecture provides a solution for high-fidelity Doppler detection in resource-constrained real-time radar applications, effectively balancing the demands of precision and efficiency.