A PHIL Controller Design Automation Method for Grid-Forming Inverters with Much Reduced Computational Delay

Within a power hardware-in-the-loop (PHIL) controller design automation (CDA) framework for voltage feedback grid-forming inverters, a scaled-down inverter system is developed for time-domain response solving. This hardware-based approach effectively addresses the conflicting demands of accuracy, computational efficiency, and modeling cost that are commonly encountered in simulation-based methods. Conventional synchronous sampling in digitally controlled pulse-width modulation (PWM) inverters introduces severe low-frequency distortion and significant ripple components in the step response, leading to non-decaying oscillations that compromise the extraction of settling time and steady-state error. By analyzing the sideband aliasing mechanism in capacitor-voltage sampling and associated harmonic-cancellation conditions, aliasing-free sampling is achieved using 90° phase-shifted anti-aliasing filters combined with synchronous sampling. Although Fast Fourier Transform (FFT) filtering offers the highest fidelity, it suffers from window-boundary distortions and is unsuitable for online use; therefore, four practical filtering schemes are evaluated against the FFT benchmark, among which oversampling with moving-average filtering (MAF) retains dynamics closest to the FFT result while avoiding its distortions. An objective function incorporating step-response metrics is constructed to optimize single-variable active damping and multiple resonant controllers, mitigating severe overshoot encountered in conventional integral-based approaches. Experimental results verify the aliasing mechanism and the effectiveness of the proposed CDA method.