PWM Technique for Improving Neutral Point Voltage Balancing in 3-level Inverters at High Modulation Ratios

This paper proposes a neutral point (NP) voltage balancing control technique for 3-level inverters operating at high modulation ratios. Compared to 2-level inverters, 3-level inverters offer lower output voltage total harmonic distortion by generating three level output voltages through a NP clamped by DC-link capacitors. However, NP voltage imbalance occur due to current flow through the NP. While various NP voltage balancing methods have been developed, their performance typically degrades at high modulation ratios. To address this issue, this paper introduces a new pulse-width modulation (PWM) technique designed to enhance NP voltage balancing performance under high modulation conditions.