Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain

Test data compression supports reductions in test data volume and test application time. The use of multicycle scan-based tests with several functional capture cycles between scan operations supports test compaction beyond that possible with single-cycle or two-cycle tests. Multicycle tests with constant primary input sequences are used for avoiding the need to synchronize the primary input sequence with the functional clock. However, this prevents the detection of delay faults in the output cone of the primary inputs. A different solution is to produce the primary input sequence of a multicycle test by the on-chip decompression logic in addition to the scan-in state. This approach is considered in this article. The key new contribution of the article is to extend the scan chain that drives the primary inputs and add design-for-testability ( DFT ) logic, to ensure that the primary input sequences produced by the decompression logic are suitable for the application of multicycle tests. Experimental results for transition faults in benchmark circuits demonstrate significant fault coverage improvements and significant test compaction.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2025-11-28
DOI
https://doi.org/10.1145/3779068
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain

Irith Pomeranz
ACM Transactions on Design Automation of Electronic Systems
VLSI and Analog Circuit Testing
article

Multicycle Tests with Compressed Primary Input Sequences and an Extended Primary Input Scan Chain

Irith Pomeranz
article en

Abstract

Test data compression supports reductions in test data volume and test application time. The use of multicycle scan-based tests with several functional capture cycles between scan operations supports test compaction beyond that possible with single-cycle or two-cycle tests. Multicycle tests with constant primary input sequences are used for avoiding the need to synchronize the primary input sequence with the functional clock. However, this prevents the detection of delay faults in the output cone of the primary inputs. A different solution is to produce the primary input sequence of a multicycle test by the on-chip decompression logic in addition to the scan-in state. This approach is considered in this article. The key new contribution of the article is to extend the scan chain that drives the primary inputs and add design-for-testability ( DFT ) logic, to ensure that the primary input sequences produced by the decompression logic are suitable for the application of multicycle tests. Experimental results for transition faults in benchmark circuits demonstrate significant fault coverage improvements and significant test compaction.

ACM Transactions on Design Automation of Electronic SystemsVol. 31(2)
Purdue University West Lafayette (US)
Openalex Percentile: Top 59%
VLSI and Analog Circuit Testing
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