Statistical Sequential Path Delay Variation Model with Lognormal Distribution for Low-Voltage Circuit

To solve the timing uncertainty in low-voltage circuits, this paper proposes an analytical sequential path delay model based on the lognormal distribution. Unlike previous works that primarily focus on combinational logic, our model provides a complete framework for sequential elements. It decouples inter-stage correlations within flip-flops through a linear delay transformation. The model’s key innovation is a one-shot characterization approach that dramatically reduces simulation time compared to traditional Monte Carlo methods. All experiments on the TSMC 28 nm process show high accuracy, with average errors below 6% against MC. Our model demonstrates significant prediction accuracy improvements of up to 10.2X over prior art, establishing a highly efficient and accurate solution for variation-aware sequential timing analysis.