Efficient Negative Weight Realization for Analog Nonlinear Resistive Neural Networks

Most analog nonlinear resistive neural networks for machine learning training use doubling input and output neuron nodes to implement negative weights. However, this approach increases network size, modifies the gradient computation, and complicates circuit design. We propose an alternative circuit topology that retains a one-to-one correspondence between neurons in the original model and their analog counterparts. Our design employs a single input source for all first-layer weights, a single resistor per weight, and a bidirectional amplifier for the rest of the layers' weight to handle negative connections without duplicating neurons. We validate our design on a binary XOR classification task over 100 training epochs and 100 randomized initializations. Our single-resistor approach achieved an average final error of -6.6 dB and required approximately 568 minutes of total CPU time. In comparison, the doubled-node design reached -4.6 dB error and consumed around 1104 minutes of CPU time. This equates to nearly <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$49\%$</tex> less computation for the single-resistor circuit while preserving the standard gradient update procedure—demonstrating that negative weights can be realized more efficiently without doubling input/output neurons.