On the Hardware Implementation of Lala's 64-bit SEcDED Codes

Protecting memories, and particularly caches, is necessary for devices running in harsh environments. The standard approach, and for good reason, is to use single-error correction, double-error detection (SECDED) codes. Among the solutions, the codes introduced by Lala have not received a lot of attention, because they cost one more bit in memory. However, for the 64-bit word granularity, they feature the lowest number of ‘1’ in their parity check matrices, which translates in less logical operations for encoding and correcting. This paper covers the design space of Lala‘s codes from a practical point of view, through synthesis on a mature silicon technology. We in particular show that the circuit timing, area, and power characteristics highly vary with the actual matrix, which allows to devise what could be the most appropriate matrix for a given set of system level constraints.