Robust Design of Power Hardware-in-the-Loop Interfacing Algorithms using Passivity Theory

Power Hardware-in-the-Loop (PHIL) has gained popularity in academic and industrial applications due to its flexibility in testing hardware. PHIL connects a physical hardware under test (HuT) to a real-time simulation via an interface that includes an interfacing algorithm (IA) and a power amplifier. Developing this interface is challenging due to the limited bandwidth of the components and delays in the system, although there are many approaches in the literature. Most face limitations when considering applications where the characteristics of the HuT are unknown. But a well-designed interface is crucial for stable and accurate operation. Based on the idea of passivity theory, this paper proposes an assessment and design method that helps to implement a robust IA. The aim is to shape the input impedance of the PHIL setup without HuT in such a way that it provides sufficient positive damping. The concept is illustrated using an example and verified with the help of simulations.