A 0.6-V All-Digital Temperature Sensor with Reduced Supply Sensitivity

The present work introduces a 0.6-volt, all-digital, synthesizable temperature sensor characterized by reduced sensitivity to supply voltage variations. The design incorporates two distinct logic delay lines that are distinguished by their equivalent transistor lengths. These variations in transistor lengths result in varying threshold voltages and thermal dependencies. The difference in thermal dependency is detected through the ratio of their charging currents, which are subsequently transformed into digital outputs via their propagation delays. By employing two types of delay lines, the sensor achieves an eightfold reduction in power supply sensitivity compared to configurations utilizing a single delay line and also obviates the necessity for an external clock. Fabricated with 55 nm CMOS technology, the proposed sensor exhibits an inaccuracy of ±1 °C, evaluated through global linear fitting and two-point calibration across five chips, within a temperature range of 20 to 90 °C. The all-digital temperature sensor consumes 2 nanojoules (nJ) for each conversion, with a conversion duration of 0.8 milliseconds (ms) and a resolution of 0.2 °C. The prototype's physical dimensions are 37 × 31 μm2. Additionally, synthesis on a Cyclone IV FPGA reveals similar characteristics in terms of supply sensitivity reduction.