A Pole‐Optimized Current‐Domain DT‐DSM With Extended Dynamic Range and High Linearity

ABSTRACT This paper presents a current‐domain discrete‐time delta‐sigma modulator (DT‐DSM) featuring a differential current integrator as primary loop filter. The proposed DT‐DSM achieves three advantages: (1) direct current quantization implementation; (2) suppression of even‐order harmonics through single‐ended current‐to‐differential‐voltage conversion; and (3) enhanced energy efficiency via elimination of front‐end signal preprocessing modules. To address the difficulty of maintaining linearity across wide dynamic ranges, this paper proposes a pole optimization technique that extends the input signal dynamic range by adjusting the pole distribution of the noise transfer function via a tunable capacitor bank. Implemented in 180‐nm CMOS technology with 2.5‐V supply voltage, the modulator consumes 3.68‐mW power. In large‐signal operation (with the pole optimization disabled), the modulator achieves 133‐dB SNDR at 10‐A input swing. With pole optimization enabled, the modulator achieves 131‐dB SNDR at 0.5‐A input swing in small‐signal operation, while maintaining 117‐dB SNDR at 80‐nA input swing. With a 1200‐Hz bandwidth, the modulator achieves a Schreier figure of merit of 186 dB.