A New Alternative to Self-Aligned Double Patterning: Pitch Splitting by Atomic Layer Etching

We have developed a method to split nanostructures in half by a single process step using Atomic Layer Etching Pitch Splitting. This method, APS TM , is a new and alternative process approach to Self-Aligned Double Patterning (SADP). In advancing cost-effective sub-20-nm feature patterning, APS TM integrates atomic level-controlled processes such as ALE with existing production technologies in a manner that enables the use of feature sidewalls for selective etching (1) without the multiple deposition and etch steps necessary in SADP processes. This provides unprecedented precision and patterning fidelity, which is key in defining critical on-device features. Previously we demonstrated the feasibility of APS TM using Si and GaP nanowires horizontally and randomly distributed over semiconductor surfaces (1). In this work demonstrate the APS TM process using lines lithographically patterned by electron beam lithography (EBL) on 300-mm silicon wafers. We achieve a half-pitch of 20 nm and critical dimensions (CDs) below 15 nm on both single- crystalline and amorphous silicon (a-Si) wafers (Figure 1). Additionally, with APS TM on GaP wafers, we achieve 3 nm CDs (Figure 2). Next, the layers split by the APS TM process can be used as a universal APS TM split mask to enable successive transfer-etch into various materials, including dielectrics, metals, metal nitrides, and high-k dielectrics. Alternatively, the resulting structures after the APS TM process can be directly used for defining critical device features, e.g. fins for fin field-effect transistors (FinFETs) and other 3D FET-structures. Characteristic is the soft-etch nature of the APS TM process, which allows minimal underlying material damage, as demonstrated by high-resolution transmission electron microscopy (HRTEM); see the image in Figure 2. Our novel patterning approach is free of some problems typical for SADP processes, such as shrinkage, “bird’s beak”, tilting, and kinking (2). This suggests that APS TM can be repeated multiple times with a high yield providing unprecedented patterning resolution for future semiconductor technology nodes. Importantly, we estimate that the APS TM process has the potential to reduce leading-edge logic and memory wafer manufacturing costs by up to 40 % per mask layer (will be presented) while concurrently increasing the throughput. This efficiency positions the APS TM process as both competitive and complementary to established patterning technologies such as self-aligned multiple patterning (SAMP, e.g. SADP), and multiple lithography-etch processes (e.g. LELE). APS TM also offers a sustainable solution to industry demands for time and resource conservation and reduced CO 2 eq. emissions. __________________________________________________________________________________________________________________________ References 1) M.S.A. Khan, J. Sundqvist and D. Suyatin, Method for selective etching of nanostructures, US Patent 10,930,515, Feb. 23, 2021; and ibid , US Patent 11,424,130, Aug. 23, 2022. 2) R.A. Farrell, E. Franke, K. Tapily, J. Hotalen, D. O'Meara, A. Raley, A. Ko, P. Biolsi, C. Wajda, G. Leusink, DeVilliers, D. Hetzer, Multi-color fly-cut-SAQP for reduced process variation , Proc. SPIE, 1058611 (2018). https://doi.org/10.1117/12.2303004 Acknowledgments EBL patterned 300-mm wafers were provided by Fraunhofer IPMS Center Nanoelectronic Technologies (CNT) in Dresden, Germany. This work has been financed by Ascent + European Union's Horizon 2020 Research and Innovation Program under GA No. 871130. Figure 1