<i>(Invited)</i> Source/Drain Epitaxy and Contact Silicides for CFET Applications

Continuous device scaling has led the microelectronic industry to intensify research efforts towards exploiting 3D devices and architectures. In this context, the advent of nanosheet (NS) devices and their stacking within complementary field effect transistors (CFET) configurations poses numerous integration challenges. E.g., source/drain (SD) epitaxy no longer proceeds from Si(001) substrates. Instead, the SD layers grow laterally on NS having Si(110) surfaces. This requires optimizing the properties of Si 1-x Ge x :B and Si:P layers grown with limited thermal budgets on non-{001} oriented Si surfaces surrounded by dielectrics. Moreover, process complexities and loading effects linked to unprecedentedly high aspect ratios and device densities need to be accounted for. Also, metal deposition processes and silicide reactions must be accurately controlled to produce extremely scaled contact resistivities while preserving the integrity of structures pre-existing on the chip. In this regard, this contribution presents the development of SD selective epitaxial growth (SEG) and alternative silicide formation processes at low temperatures (LT) for upcoming technology nodes. LT chemical vapour deposition allows to grow SD epilayers with high active doping concentrations [1]. This enables the formation of contacts with low specific resistivities. Challenges linked to the non-selective nature of such growth processes can be overcome by combining these with the selective etching of unwanted parasitic components within cyclic deposition and etch routines. A fine tuning of the deposition and etch times enables the SEG of lowly resistive Si:P from {110} NS sidewalls below 500°C [2] (Fig 1(a)). As a complement, the current paper provides demonstrations of LT (400°C) SiGe:B SEG in a similar context (Fig 1(b)). Little has been reported so far on the impact of substrate orientation and scaling on the resulting SD properties. A comparison of Si 1-x Ge x :B layers grown on Si(001), Si(110) and Si(111) is hence proposed. It highlights the existence of different optimized process windows on those surfaces. Notably, for Si 0.4 Ge 0.6 :B epitaxy at 500°C, resistivities are the lowest for Si 0.4 Ge 0.6 :B / Si(111), down to 1.2x10 -4 ohm.cm, which corresponds to a 60% decrease with respect to Si 0.4 Ge 0.6 :B / Si(001) [3]. This behavior however depends on the growth conditions. Systematic assessments are thus performed to derive guidance for device processing. The resistivity of Ti, Sc and Mo based contacts deposited on Si(001), Si(110) and Si(111) is not significantly affected by the surface orientation [3]. However, forming silicides on SD surfaces with different compositions may greatly impact the obtained crystalline phases [4,5]. Sc contacts to LT Si:P / Si(001) for instance exhibit remarkable structural properties, driven by the LT formation of a cubic P-rich Sc 1−x−y Si x P y interfacial layer being commensurate with Si:P containing 3% P (Fig 1(c)). [1,4]. This results in extremely low contact resistivities for NMOS, as extracted using circular transmission line model (CTLM) patterned structures. On the other hand, Mo contacts deposited on p-type Si 1-x Ge x do not readily form (germano)silicides (Fig 1(d)), despite also providing excellent contact properties. Comparisons with alternative contact stacks are therefore proposed to unravel the mechanisms responsible for these attractive properties and provide options suitable for modern CMOS devices. References [1] C. Porret et al. , IEEE International Electron Devices Meeting (IEDM), 2022 [2] E. Rosseel et al. , ECS Transactions, 109, 93, 2022 [3] C. Porret et al. , Materials for Advanced Metallization conference (MAM), 72, 2025 [4] B. Pollefliet et al., Japanese Journal of Applied Physics, 63, 02SP97, 2024 [5] B. Pollefliet et al., Materials for Advanced Metallization conference (MAM), 70, 2025 Acknowledgements This work has been enabled in part by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit nanoic-project.eu. The imec core CMOS program members, local authorities and the imec pilot line are acknowledged for their support. All epitaxial materials presented in this work are grown in ASM Intrepid ® CVD reactors. Air Liquide Advanced Materials is acknowledged for providing Ge 2 H 6 . Figure 1