DeepRoute: A Fast FPGA Routing Algorithm Using Graph Embedding for Node Filtering

In this paper, we present DeepRoute, an improved FPGA routing algorithm that introduces graph embedding into FPGA routing to accelerate this most time-consuming stage of the FPGA design flow. By adapting the random walk method with simple yet effective modifications, high-quality graph embeddings are generated. These embeddings enable the filtering of unpromising nodes, significantly reducing the router’s search space. To further enhance DeepRoute’s performance, two engineering enhancements are implemented, timing criticality constraints and detailed search regions. Experimental results show that DeepRoute achieves routing speedups of 51.31% over Verilog-to-Routing 8 (VTR8), rising to 54.25% for larger circuits, while maintaining timing performance and acceptable wirelength changes.