A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis

High-Level Synthesis (HLS) has gained considerable attention for its ability to quickly generate hardware descriptions from untimed specifications. Most state-of-the-art commercial HLS tools employ static scheduling, which excels in compute-intensive applications but struggles with control-dominant designs. While some open-source tools propose dynamic and hybrid scheduling techniques to synthesize dataflow-like architectures to improve speed, they lack well-established optimizations from static scheduling like datapath optimization and resource sharing, leading to frequency degradation and area overhead. Moreover, existing hybrid scheduling relies on extra dynamic synthesis support, either by dynamic or static HLS tools, and thereby loses generality. In this work, we propose another solution to achieve hybrid scheduling: a source-to-source compiler that exposes dynamism at the source code level, which reduces both frequency and area overhead while remaining fully compatible with modern static HLS tools without needing extra dynamic synthesis support. Experiments show significant improvements (1.26× speedup) on wall clock time (WCT) compared to VitisHLS and a better area–frequency–latency trade-off compared to dynamic (1.83× WCT speedup and 0.46× area) and hybrid (2.14× WCT speedup and 0.72× area) scheduling-based tools.

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Publication Details

Journal
Electronics
Published
2025-11-22
DOI
https://doi.org/10.3390/electronics14234578
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00

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article

A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis

Yuhan She, Ray C. C. Cheung, Hong Yan, Yanlong Huang et al.
Electronics
Embedded Systems Design Techniques
article

A Source-to-Source Compiler to Enable Hybrid Scheduling for High-Level Synthesis

Yuhan She, Ray C. C. Cheung, Hong Yan, Yanlong Huang, Jierui Liu
article en

Abstract

High-Level Synthesis (HLS) has gained considerable attention for its ability to quickly generate hardware descriptions from untimed specifications. Most state-of-the-art commercial HLS tools employ static scheduling, which excels in compute-intensive applications but struggles with control-dominant designs. While some open-source tools propose dynamic and hybrid scheduling techniques to synthesize dataflow-like architectures to improve speed, they lack well-established optimizations from static scheduling like datapath optimization and resource sharing, leading to frequency degradation and area overhead. Moreover, existing hybrid scheduling relies on extra dynamic synthesis support, either by dynamic or static HLS tools, and thereby loses generality. In this work, we propose another solution to achieve hybrid scheduling: a source-to-source compiler that exposes dynamism at the source code level, which reduces both frequency and area overhead while remaining fully compatible with modern static HLS tools without needing extra dynamic synthesis support. Experiments show significant improvements (1.26× speedup) on wall clock time (WCT) compared to VitisHLS and a better area–frequency–latency trade-off compared to dynamic (1.83× WCT speedup and 0.46× area) and hybrid (2.14× WCT speedup and 0.72× area) scheduling-based tools.

ElectronicsVol. 14(23)
City University of Hong Kong (HK), Hong Kong Science and Technology Parks Corporation (HK)
Innovation and Technology Commission
Openalex Percentile: Top 60%
Embedded Systems Design Techniques
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