Model of 22 nm FDSOI MOSFET and digital cell characteristics at cryogenic temperature

Abstract This paper presents a cryogenic simulation model for 22 nm ultra-thin box and body fully depleted silicon-on-insulator (UTBB-FDSOI) MOSFETs, calibrated using TCAD model and measurements at cryogenic temperatures (CT) from 300 K to 4.5 K. To account for cryogenic effects, SPICE model parameters related to the physical mechanisms were adjusted on the basis of TCAD simulations and test chip measurements. Meanwhile, the capacitance change of 22 nm FDSOI MOSFET at CT is explored and validated from the TCAD model and circuits. The validated cryogenic SPICE model was used to assess the impact of cryogenic conditions on digital logic circuits, analyzing both static and dynamic CMOS logic to guide low power and high speed design at CT.