Scaling the Area of Synthesizable FPGA Tiles Across Semiconductor Process Nodes

Synthesizable field-programmable gate arrays (FPGAs) have recently gained significant traction due to their low development costs and their ability to adapt to new process technologies. The successful adoption of synthesizable FPGAs requires robust methodologies for estimating the area characteristics of the FPGA tiles in the synthesizable FPGA fabrics. FPGA tile area is used to determine the physical lengths of an FPGA’s routing segments and is therefore crucial to ensuring the accurate benchmarking of newly proposed FPGA architectures. In this work, we present a methodology to estimate the area of synthesizable FPGA tiles across various semiconductor process technologies. The methodology leverages scaling trends in the area of synthesizable FPGA tiles and selected hierarchical blocks to derive scaling factors that can be used to scale the area of synthesizable FPGA tiles across process nodes. The results demonstrate that this methodology achieves a maximum absolute percentage error of less than 10% when scaling the area of synthesizable FPGA tiles across open-sourced 130 nm, 45 nm, 15 nm and 7 nm process nodes.