ICON-NIV: A Generalized Method for Mitigating the Impacts of IR Drop and Nonlinear I-V Effect in eNVM-based Accelerators.

Computing in emerging non-volatile memory (eNVM)-based accelerators is promising for efficient matrix-vector multiplication (MVM), and many previous accelerators compute at operating unit (OU) granularity to mitigate the program variation effect. Unfortunately, computing at OU granularity, like the entire array, still suffers from the impacts of non-idealities, i.e., the IR drop and nonlinear I-V effect (IR-NIV). These nonidealities significantly compromise computing accuracy. Even worse, the dependence of IR-NIV undermines the effectiveness of existing IR drop and nonlinear I-V compensation methods, as well as their combination. The IR drop first reduces the voltage across an eNVM cell, which in turn causes a variation in the cell conductance due to nonlinear I-V. Neither the IR drop nor the nonlinear I-V compensator can acquire the actual voltage or cell conductance due to the dependence of IR-NIV, leading to inaccurate results. This article proposes ICON-NIV, a generalized method for mitigating the impacts of both IR drop and nonlinear I-V effect in eNVM-based accelerators. First, we build an OU-level IR drop model by removing wire resistances inside the OU, and simplify the complex nonlinear I-V model of the cell into the optimal segmented linear interpolation while maintaining sufficient precision. With the aid of the simplifications above, we derive the theoretical compensation math expression for the output result considering the coupling effects of IR-NIV, and build the corresponding compensation circuit. The compensation expression uses the output of the OU column to calculate the actual cell voltage with the simplified OU-level IR drop model. And with the aid of the simplified cell I-V model, the actual cell conductance under the impacts of the nonlinear I-V effect is calculated using the actual cell voltage. After acquiring the actual cell voltage and conductance, ICON-NIV can precisely compensate for output loss. Moreover, the compensation expression takes the input and data pattern of an OU as arguments instead of the specific application features, which is applicable to all kinds of applications. Furthermore, we pipe the compensation circuit into multiple stages to increase throughput. Experiments show that ICON-NIV can mitigate the IR-NIV problem when computing in the eNVM crossbar array at OU granularity, restoring inference accuracy by 3.03% \(\sim\) 71.90% (for neural networks and naive Bayes), and achieving a reduction in mean-squared error by \(10^{14}\times\) (for scientific computing), compared with the state-of-the-art methods. The latency of each stage of the compensation circuit is 7.21 ns, which closely matches the computation latency of the original OU operation.

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Journal
ACM Transactions on Architecture and Code Optimization
Published
2025-11-24
DOI
https://doi.org/10.1145/3777381
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
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article

ICON-NIV: A Generalized Method for Mitigating the Impacts of IR Drop and Nonlinear I-V Effect in eNVM-based Accelerators.

Xueliang Wei, Jinpeng Liu, Dan Feng, Bing Wu et al.
ACM Transactions on Architecture and Code Optimization
Parallel Computing and Optimization Techniques
article

ICON-NIV: A Generalized Method for Mitigating the Impacts of IR Drop and Nonlinear I-V Effect in eNVM-based Accelerators.

Xueliang Wei, Jinpeng Liu, Dan Feng, Bing Wu, Heng Zhou, Huan Cheng, Wei Tong
article en

Abstract

Computing in emerging non-volatile memory (eNVM)-based accelerators is promising for efficient matrix-vector multiplication (MVM), and many previous accelerators compute at operating unit (OU) granularity to mitigate the program variation effect. Unfortunately, computing at OU granularity, like the entire array, still suffers from the impacts of non-idealities, i.e., the IR drop and nonlinear I-V effect (IR-NIV). These nonidealities significantly compromise computing accuracy. Even worse, the dependence of IR-NIV undermines the effectiveness of existing IR drop and nonlinear I-V compensation methods, as well as their combination. The IR drop first reduces the voltage across an eNVM cell, which in turn causes a variation in the cell conductance due to nonlinear I-V. Neither the IR drop nor the nonlinear I-V compensator can acquire the actual voltage or cell conductance due to the dependence of IR-NIV, leading to inaccurate results. This article proposes ICON-NIV, a generalized method for mitigating the impacts of both IR drop and nonlinear I-V effect in eNVM-based accelerators. First, we build an OU-level IR drop model by removing wire resistances inside the OU, and simplify the complex nonlinear I-V model of the cell into the optimal segmented linear interpolation while maintaining sufficient precision. With the aid of the simplifications above, we derive the theoretical compensation math expression for the output result considering the coupling effects of IR-NIV, and build the corresponding compensation circuit. The compensation expression uses the output of the OU column to calculate the actual cell voltage with the simplified OU-level IR drop model. And with the aid of the simplified cell I-V model, the actual cell conductance under the impacts of the nonlinear I-V effect is calculated using the actual cell voltage. After acquiring the actual cell voltage and conductance, ICON-NIV can precisely compensate for output loss. Moreover, the compensation expression takes the input and data pattern of an OU as arguments instead of the specific application features, which is applicable to all kinds of applications. Furthermore, we pipe the compensation circuit into multiple stages to increase throughput. Experiments show that ICON-NIV can mitigate the IR-NIV problem when computing in the eNVM crossbar array at OU granularity, restoring inference accuracy by 3.03% \(\sim\) 71.90% (for neural networks and naive Bayes), and achieving a reduction in mean-squared error by \(10^{14}\times\) (for scientific computing), compared with the state-of-the-art methods. The latency of each stage of the compensation circuit is 7.21 ns, which closely matches the computation latency of the original OU operation.

ACM Transactions on Architecture and Code OptimizationVol. 23(1)
Wuhan National Laboratory for Optoelectronics (CN), Huazhong University of Science and Technology (CN)
Openalex Percentile: Top 60%
Parallel Computing and Optimization Techniques
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