Design and analysis of 3D stacked nanosheet-based capacitorless DRAM with separated storage regions under process variations

Conventional one-transistor–one-capacitor (1T–1C) dynamic random-access memory (DRAM) faces significant challenges in achieving high integration and cell-area scaling due to physical limitations in maintaining the size and shape of the cell capacitor. As device scaling progresses, securing sufficient capacitance becomes increasingly difficult, necessitating the fabrication of high–aspect-ratio capacitors. This requirement, in turn, increases process complexity and manufacturing cost. To address these limitations, this study proposes a gate-all-around (GAA) nanosheet (NS)–based capacitorless DRAM (1T-DRAM) structure, in which the current conduction path and the hole storage region are physically separated. The proposed device was evaluated through simulations that examined structural variations, such as taper angle and Si edge rounding induced by vertical stacking and etching, as well as electrical disturbances during memory array operation to assess device reliability. Simulation results indicate that smaller taper angles and increased Si edge rounding reduce the effective channel width, leading to an increased sensing margin (SM) but a decreased retention time (RT). This behavior is attributed to variations in stored hole density. The proposed structure also shows heightened sensitivity to taper angle variation, underscoring the importance of precise reactive-ion etching (RIE) control. Furthermore, under electrical array disturbance conditions, the proposed 1T-DRAM maintains stable operation, exhibiting variations of less than ±2% in SM and ±6% in RT, demonstrating its robustness. These findings highlight the potential of the proposed architecture for realizing highly integrated and reliable memory devices.